1. Field of the Invention
This invention is related to testing integrated circuits and, more particularly, to identifying speed paths for correction to permit subsequent revisions of the integrated circuit to operate at a higher frequency.
2. Description of the Related Art
Integrated circuits of various types are becoming part of numerous products across many different industries. As integrated circuit fabrication processes have continued to shrink, the size of devices that can be fabricated on a semiconductor substrate (e.g. transistors) has shrunk and thus the number of devices included on a given integrated circuit (or “chip”) has skyrocketed. Accordingly, designing and testing the chips to ensure quality, error-free operation and to ensure high manufacturing yields at a desired operating frequency has become more challenging.
During the design phase of an integrated circuit, various timing tools are typically utilized to estimate the timing of the circuitry (and thus to estimate the highest clock frequency at which the integrated circuit would operate correctly). For example, static timing analysis tools, Spice simulations, etc. are used during the design phase. However, all such tools are estimates of the actual operation of the circuit. Some paths that are identified as having slow timing may be faster than estimated, and other paths may be slower than estimated. Additionally, factors that are not accounted for in the tools may change the timing characteristics of various paths.
After a version of the integrated circuit design is “taped out” and fabricated, real circuitry is available for testing and characterization. One form of testing is speed path debugging. In speed path debugging, various test patterns are run at various desired clock frequencies (or at various increasing clock frequencies) to locate the circuit paths (speed paths) that limit the clock frequency. That is, the test patterns are executed on the integrated circuit and, if a failure is detected, the failure is analyzed to locate the speed path that is causing the failure. For example, once a failure is identified at a particular clock cycle of the test pattern, the test pattern is executed at a lower (passing) frequency and the state of the integrated circuit at the failing clock cycle and nearby clock cycles is scanned out (e.g. all the state in various flops and other clocked storage devices that are attached to scan chains in the integrated circuit is scanned out). The test pattern can also be executed at the failing frequency, and the state can be scanned out again for the same clock cycles. By comparing the passing and failing state, the circuitry that is causing the failure can be identified with a reasonable degree of specificity. By improving the timing characteristics of the speed path (e.g. by changing the circuitry, reducing the load on the path, etc.) in a subsequent version of the integrated circuit, the speed path may no longer limit the frequency or may permit a higher frequency than in the previous version.
The above procedure allows one speed path to be detecting for a given test pattern. There may be other speed paths that could occur later in the test pattern, or that could be slightly faster than the identified speed path and thus cannot be detected. One mechanism used to allow further testing is “stretch mode”. In stretch mode, the test pattern is run at speed except for the failing clock cycle, which is “stretched” (made longer) so that the speed path doesn't cause a failure. For example, the clock frequency may be halved for the failing clock cycle, doubling the clock period for the failing clock cycle. Potentially, other speed paths can be identified. In some cases, a subsequently identified failure may be the same speed path that has been previously identified.
Other mechanisms for testing exist. For example, the AMD Athlon™ processors include a pattern generator that receives the clock output of the phase locked loop (PLL) and can be programmed to provide a pattern on the clock provided to the clocked storage devices. That pattern can change on a cycle by cycle basis (e.g. ½ frequency, ¼ frequency, etc.). For example, a 64 clock cycle pattern could be programmed into the pattern generators.